1. Field of the Invention
This invention relates to a method for fabricating memory, and more particularly, to a method for fabricating flash memory.
2. Description of Related Art
Electrically erasable programmable read-only-memories (EEPROMs) are widely used as memory components for personal computers and electronic equipment. A conventional EEPROM memory cell comprises a floating gate transistor structure that is programmable, erasable and able to store data. However, the conventional EEPROM suffers from a slow storage and retrieval time of typically around 150-200 ns. Recently, a faster EEPROM, for example, a flash memory, has been developed with a storage and retrieval time of about 70-80 ns.
A conventional floating gate transistor relies on hot electrons and Fowler-Nordheim tunneling to store and erase data. For example, when the flash memory stores data, a high voltage, on the order of 8 volts, is applied between the source region and the drain region. A high voltage is also applied to the control gate. Hot electrons generated near the drain region will flow toward the floating gate through the tunneling oxide layer. By this mechanism, the threshold voltage of the floating gate transistor is raised to store data.
When the data is to be erased, a negative voltage is applied to the control gate and a positive voltage applied to the source region. The electrons trapped in the floating gate tunnel through the tunneling oxide layer to erase the data, and the floating gate returns to the uncharged state. In the erasing process, the erasing time takes a long time to ensure the uncharged state of the floating gate.
FIG. 1 is a schematic layout of a conventional flash memory. FIGS. 2 to 4 are cross-sectional views taken along the line I--I in FIG. 1, schematically illustrating the fabrication process. FIGS. 5 to 6 are cross-sectional views taken along the line II--II in FIG. 1, schematically illustrating the fabrication process. The manufacturing method of the conventional flash memory is described below.
In FIGS. 2 and 5 a pad oxide layer (not shown) is first formed by thermal oxidation on a substrate 10. Active regions are then defined by forming field oxide layer 14, using local oxidation. The pad oxide layer is then removed by wet etching. Next, a tunneling oxide layer 12 with a thickness of about 100 .ANG. is formed on the surface of the device regions by thermal oxidation. Then, a polysilicon layer is formed on the tunneling oxide layer 12 by low pressure chemical vapor deposition (LPCVD). The polysilicon layer is then defined by photolithography and etching to form a polysilicon layer 16 with a thickness of about 1500 .ANG..
Next, an inter-poly dielectric layer is formed by, for example, LPCVD, and covers the polysilicon layer 16. The inter-poly dielectric layer has a thickness of about 250 .ANG. and includes oxide/nitride/oxide layers. Then, another layer of polysilicon with a thickness of about 3000 .ANG. is formed on the polysilicon layer 16. Both the inter-poly dielectric layer and the polysilicon layer are patterned by photolithography and etching to become an inter-poly dielectric layer 18 and polysilicon layer 20. The polysilicon layer 20 is utilized as a control gate of the flashing memory.
Then, by using the polysilicon layer 20 as a mask, the polysilicon layer 16 is further patterned by etching. A process of implanting ions is next performed by using the polysilicon layer 20 as a mask to form an implantation region 22 with a higher density of doped ions than that of the substrate. A gate electrode of the flash memory includes the polysilicon layer 20, inter-poly dielectric layer 18, polysilicon layer 16 and tunneling oxide layer 12.
Thereafter, the semiconductor substrate is patterned by using a mask (not shown), exposing the implantation region, 22 located at one side of the gate electrode. A process of implanting ions is next performed by using a tilted angle to implant dopant into substrate 10, and a process of annealing is performed to form a diffusion region 24. The diffusion region 24 is located around the implantation region 22, and extends underneath the gate electrode. The implantation region 22 is surrounded by the diffusion region 24. The mask (not shown) is removed after the diffusion region 24 is formed.
Referring to FIG. 3, a layer of oxide is deposited over the whole surface of the substrate structure by using LPCVD. An etching back method is then performed on the oxide layer to form spacers 26 on sidewalls of the gate electrode. Thereafter, an implantation region 28 is formed by implanting ions into the substrate 10 as illustrated in FIG. 3. The cross-sectional view taken along the line II--II in FIG. 3 is still the same as FIG. 5.
Referring to FIGS. 4 and 6, a dielectric layer 30 is formed over the whole substrate structure by using LPCVD. A contact opening 32 is formed on the dielectric layer 30 by lithography and etching to expose the implantation region 22. Then, a metal layer 34 acting as a bit line is formed over the dielectric layer 30 by LPCVD, filling the contact opening 32 so that the metal layer 34, also known as the bit line, is electrically coupled to the implantation region 22. Fabrication of the flash memory is completed in a conventional procedure. This procedure is familiar to those skilled in the art and therefore is not described here.
In the conventional method described above, it is difficult to effectively reduce the flash memory size because it is limited by the contact opening. The existence of the field oxide layer 14 also affects the size reduction and planarization of the active region. Additionally, since the metal layer 34 also has to fill the contact opening 32 in order to serve as the bit line, interference due to signal reflection from the metal layer 34 is inevitable.